Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components. For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
Through Silicon Via (TSV) provides communication links for chips in vertical direction to facilitate increased level of integration in packaging and it can be used in three-dimensional integrated circuit (3D IC). Three-dimensional integrated circuits (3DICs) may be formed by stacking two dies together, with TSVs formed in one of the dies to connect the other die to a package substrate. Generally, TSVs are formed in a semiconductor wafer by initially forming an opening partially through a substrate, and filling the opening with a conductive material, such as copper. TSVs are much larger than other standard cells in a design, and thus impact IC performance in a greater degree.
Devices in the vicinity of TSVs suffer serious performance degradation due to the stress induced by the TSVs. To minimize such performance variation, a Keep-Out Zone (KOZ) is imposed around a TSV where no other devices can be placed within a KOZ. The higher the KOZ is, the lower the silicon area utilization is.